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HSP45256
Data Sheet May 1999 File Number
2814.4
Binary Correlator
The Intersil HSP45256 is a high-speed, 256 tap binary correlator. It can be configured to perform one-dimensional or two-dimensional correlations of selectable data precision and length. Multiple HSP45256's can be cascaded for increased correlation length. Unused taps can be masked out for reduced correlation length. The correlation array consists of eight 32-tap stages. These may be cascaded internally to compare 1, 2, 4 or 8-bit input data with a 1-bit reference. Depending on the number of bits in the input data, the length of the correlation can be up to 256, 128, 64, or 32 taps. The HSP45256 can also be configured as two separate correlators with window sizes from 4 by 32 to 1 by 128 each. The mask register can be used to prevent any subset of the 256 bits from contributing to the correlation score. The output of the correlation array (correlation score) feeds the weight and sum logic, which gives added flexibility to the data format. In addition, an offset register is provided so that a preprogrammed value can be added to the correlation score. This result is then passed through a user programmable delay stage to the cascade summer. The delay stage simplifies the cascading of multiple correlators by compensating for the latency of previous correlators. The Binary Correlator is configured by writing a set of control registers via a standard microprocessor interface. To simplify operation, both the control and reference registers are double buffered. This allows the user to load new mask and reference data while the current correlation is in progress.
Features
* Reconfigurable 256 Stage Binary Correlator * 1-Bit Reference x 1, 2, 4, or 8-Bit Data * Separate Control and Reference Interfaces * 25.6, 33MHz Versions * Configurable for 1-D and 2-D Operation * Double Buffered Mask and Reference * Programmable Output Delay * Cascadable * Standard Microprocessor Interface
Applications
* Radar/Sonar * Spread Spectrum Communications * Pattern/Character Recognition - Error Correction Coding
Ordering Information
PART NUMBER HSP45256JC-25 HSP45256JC-33 HSP45256GC-25 HSP45256GC-33 HSP45256JI-25 HSP45256JI-33 TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 84 Ld PLCC 84 Ld PLCC 85 Ld PGA 85 Ld PGA 84 Ld PLCC 84 Ld PLCC PKG. NO. N84.1.15 N84.1.15 G85.A G85.A N84.1.15 N84.1.15
Block Diagram
DOUT DOUT0-7 DIN0-7 DREF0-7 256 TAP CORRELATION ARRAY DREFOUT CSCORE WEIGHT AND SUM MUX AUXOUT0-8
DCONT0-7 CONTROL A0-2 DELAY CASCADE SUMMER CASOUT0-12
CASIN0-12
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HSP45256 Pinouts
85 PIN PGA BOTTOM VIEW
L DREF0 K DREF2 J DREF3 H DREF5 G DIN0 F DREF6 E DIN4 D DIN7 C CLK B GND A CASIN 2 1 CASIN 4 2 CASIN 5 3 CASIN 7 4 CASIN 10 5 CASIN CASOUT CASOUT CASOUT 3 0 5 11 6 7 8 9 GND 10 CASOUT 8 11 CASIN1 CASIN3 CASIN6 CASIN CASOUT CASOUT CASOUT CASOUT CASOUT CASOUT 7 9 2 1 4 10 CASIN0 INDEX PIN CASIN 8 CASIN 12 OEC CASOUT CASOUT 9 11 VCC GND CASOUT 12 DIN5 DIN6 DOUT0 DOUT1 DOUT2 DIN3 DIN2 DOUT4 DOUT7 DOUT3 DREF7 DIN1 VCC DOUT6 DOUT5 DREF4 AUXOUT AUXOUT 1 0 DREF1 A1 DCONT DCONT 5 4 GND AUX OUT2 VCC RLOAD CLOAD A0 DCONT DCONT 6 2 OEA AUX OUT6 AUX OUT4 AUX OUT3 GND TXFR A2 DCONT7 DCONT1 DCONT3 DCONT0 AUX OUT8 AUX OUT7 AUX OUT5
85 PIN PGA TOP VIEW
1 A CASIN 2 GND CLK 2 CASIN 4 CASIN 1 CASIN 0 VCC DIN5 DIN6 DOUT0 DOUT 4 VCC 3 CASIN 5 CASIN 3 INDEX PIN 4 CASIN 7 CASIN 6 5 CASIN 10 CASIN 9 CASIN 8 6 CASIN 11 CAS OUT2 CASIN 12 7 CAS OUT CAS OUT1 OEC 8 CAS OUT3 CAS OUT4 9 CAS OUT5 CAS OUT6 10 GND CAS OUT7 CAS OUT9 GND 11 CAS OUT8 CAS OUT10 CAS OUT11 CAS OUT12 DOUT2 DOUT 3 DOUT 5 AUX OUT0 AUX OUT2 AUX OUT3 AUX OUT5
B
C
D
DIN7
E
DIN4 DREF 6 DIN0 DREF 5 DREF 3 DREF 2 DREF 0
DOUT DOUT 7 DOUT 6 AUX OUT1
F
DIN3 DREF 7 DREF 4 DREF 1 VCC GND
DIN2
G
DIN1
H
J
A1 R LOAD TXFR C LOAD A2
DCONT 5 DCONT 6
DCONT 4 DCONT 2 OEA AUX OUT6 AUX OUT8
GND AUX OUT4 AUX OUT7
K
A0
L
DCONT DCONT 7 1
DCONT DCONT 0 3
2
HSP45256 Pinouts
(Continued) 84 PIN PLCC TOP VIEW
CASIN2 CASIN3 CASIN4 CASIN5 CASIN6 CASIN7 CASIN8 CASIN9 CASIN10 CASIN11 CASIN12 OEC# CASOUT0 CASOUT1 CASOUT2 CASOUT3 CASOUT4 CASOUT5 GND CASOUT6 CASOUT7 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 CASIN1 CASIN0 GND CLK VCC DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 DREF7 DREF6 DREF5 DREF4 DREF3 DREF2 DREF1 DREF0 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 VCC RLOAD GND TXFR CLOAD A2 A1 A0 DCONT7 DCONT6 DCONT5 DCONT4 DCONT3 DCONT2 DCONT1 DCONT0 OEA AUXOUT8 AUXOUT7 AUXOUT6 AUXOUT5 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 CASOUT8 CASOUT9 CASOUT10 CASOUT11 GND CASOUT12 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 VCC DOUT5 DOUT6 DOUT7 AUXOUT0 AUXOUT1 AUXOUT2 AUXOUT3 GND AUXOUT4
3
HSP45256 Pin Descriptions
SYMBOL VCC GND DIN0-7 PLCC PIN NUMBER 16, 33, 63 14, 35, 55, 70, 77 17-24 I TYPE The +5V power supply pin. Ground. The DIN0-7 bus consists of eight single data input pins. The assignment of the active pins is determined by the configuration. Data is loaded synchronous to the rising edge of CLK. DIN0 is the LSB. The DOUT0-7 bus is the data output of the correlation array. The format of the output is dependent on the window configuration and bit weighting. DOUT0 is the LSB. System Clock. Positive edge triggered. CASIN0-12 allows multiple correlators to be cascaded by connecting CASOUT0-12 of one correlator to CASIN0-12 of another. The CASIN bus is added internally to the correlation score to form CASOUT. CASIN0 is the LSB. CASOUT0-12 is the output correlation score. This value is the delayed sum of all the 256 taps of one chip and CASIN0-12. When the part is configured to act as two independent correlators, CASOUT0-8 represents the correlation score for the first correlator while the second correlation score is available on the AUXOUT0-8 bus. In this configuration, the cascading feature is no longer an option. CASOUT0 is the LSB. OEC is the output enable for CASOUT0-12. When OEC is high, the output is three-stated. Processing is not interrupted by this pin (active low). TXFR is a synchronous clock enable signal that allows the loading of the reference and mask inputs from the preload register to the correlation array. Data is transferred on the rising edge of CLK while TXFR is low (active low). DREF0-7 is an 8-bit wide data reference input. This is the input data bus used to load the reference data. RLOAD going active initiates the loading of the reference registers. This input bus is used to load the reference registers of the correlation array. The manner in which the reference data is loaded is determined by the window configuration. If the window configuration is 1 x 256, the reference bits are loaded one at a time over DREF7. When the HSP45256 is configured as an 8 x 32 array, the data is loaded into all stages in parallel. In this case, DREF7 is the reference data for the first stage and DREF0 is the reference data for the eighth stage. The contents of the reference data registers are not affected by changing the window configuration. DREF0 is the LSB. RLOAD enables loading of the reference registers. Data on DREF0-7 is loaded into the preload registers on the rising edge of RLOAD. This data is transferred into the correlation array by TXFR (active low). DCONT0-7 is the control data input which is used to load the mask bit for each tap, as well as the configuration registers. The mask data is sequentially loaded into the eight stages in the same manner as the reference data. DCONT0 is the LSB. CLOAD enables the loading of the data on DCONT0-7. The destination of this data is controlled by A0-2 (active low). A0-2 is a 3-bit address that determines what function will be performed when CLOAD is active. This address bus is set up with respect to the rising edge of the load signal, CLOAD. A0 is the LSB. AUXOUT0-8 is a 9-bit bus that provides either the data reference output in the single correlation configuration or the 9-bit correlation score of the second correlator, in the dual correlator configuration. When the user programs the chip to be two separate correlators, the score of the second correlator is output on this bus. When the user has programmed the chip to be one correlator, AUXOUT0-7 represents the reference data out, with the state of AUXOUT8 undefined. AUXOUT0 is the LSB. The OEA signal is the output enable for the AUXOUT0-8 output. When OEA is high, the output is disabled. Processing is not interrupted by this pin (active low). DESCRIPTION
DOUT0-7 CLK CASIN0-12
60-62, 64-68 15 1-13
O I I
CASOUT0-12
69, 71-76, 78-83
O
OEC TXFR
84 36
I I
DREF0-7
25-32
I
RLOAD
34
I
DCONT0-7
41-48
I
CLOAD A0-2
37 38-40
I I
AUXOUT0-8
50-54, 56-59
O
OEA
49
I
4
HSP45256 Block Diagram
CONFIG OFFAL A(2:0) DECODE CLOAD OFFAM DELAY OFFBL OFFBM MASK DCONT(7:0) RLOAD TXFR DO7 DIN7 R E G TC R E G MR7 32 TAP CORRELATOR STAGE RO7 DATA OUT RO7 (000) R E G 8 (001) R E G R E G 6 5 CONFIG(4:0)
>
>
TC
>
>
DREF7
>
+
R E G
CORRELATION SCORE OUT CO7
>
DO7 DO6 DIN6 R E G 32 TAP CORRELATOR STAGE CONFIG(4:0) RO7 MR6 RO6 DATA OUT RO6
>
+
DREF6
>
R E G
>
R E G
CO6
DO1 DO0 RO0
DIN0
>
R E G
32 TAP CORRELATOR STAGE CONFIG(4:0) RO1 MR0
RO0
+
DREF0
>
R E G
>
CLK
R E G MUX ARRAY
CO0
REFERENCE OUT
>G
R E
CASIN(12:0) OEA OEC
CASIN(12:0) OEA OEC DOUT(7:0)
NOTE: All registers clocked with CLK unless otherwise specified. CORRELATOR BLOCK DIAGRAM
5
HSP45256 Block Diagram
(Continued)
R E G 5
OFFSET REGISTER A OFFAM OFFAL OFFBM OFFBL DELAY
(010)
>
(011)
>
(101)
R E G R E G
8 R E G
1
>
>
(110)
>
CONFIG(4:0)
R E G
8 OFFSET REGISTER B
CORRELATION SCORE OUT CO7
4 CO6 DELAY WEIGHT R E G SUM R E G PROGRAMMABLE DELAY (100) CASOUT(12:0)
>
>
+
>
R E G
OEC
CO0 RO(0-7) REFERENCE OUT RLOAD R E G
>
R E G R E G CONFIG(4:0) OEA
AUXOUT(8:0)
>
CASCADE REGISTER
CASIN(12:0) OEA OEC DOUT(7:0)
>
DOUT(7:0)
NOTE: All registers clocked with CLK unless otherwise specified.
6
HSP45256 Functional Description
The correlation array consists of eight 32-bit stages. The first stage receives data directly from input pin DIN7. The other seven stages receive input data from either an external data pin, DIN0-6, or from the Shift Register output of the previous stage, as determined by the Configuration Register. When the part is configured as a single correlator the sum of correlation score, Offset Register and cascade input appears on CASOUT0-12. Delayed versions of the data and reference inputs appear on DOUT0-7 and AUXOUT0-7, respectively. The input and output multiplexers of the correlation array are controlled together; for example, in a 1 x 256 correlation, the input data is loaded into DIN7 and the output appears on DOUT7. The configuration of the data bits, the length of the correlation (and in the two-dimensional data, the number of rows), is commonly called the correlation window. A top level Block Diagram of the single correlator configuration is shown in Figure 1. Compare the single correlator configuration data output and correlation output to the top level Block Diagram of the dual correlator configuration shown in Figure 2.
DIN(7:0) DREF(7:0) 8 32-BIT CORRELATORS ************ SUM CORR SCORE AUXOUT(7:0) DELAY = 0000 OFFA DOUT(7:0) CORR
Correlator Array
The core of the HSP45256 is the correlation array, which consists of eight 32-tap stages. A single correlator cell consists of an XNOR gate for the individual bit comparison; i.e., if the data and reference bits are either both high or both low, the output of the correlator cell is high. Figure 3 details the circuitry of a single correlation cell and Figure 4 shows the timing for that single correlation cell. In addition, two latches, one for the reference and one for the control data path are contained in this cell. These latches are loaded from the Preload Registers on the rising edge of CLK when TXFR is low so that the reference and mask values are updated without interrupting data processing. The mask function is implemented with an AND gate. When a mask bit is a logic low, the corresponding correlator cell output is low.
DIN(7:4) DREF(7:4) DOUT(7:4)
4 32-BIT CORRELATORS ************ SUM SCORE
WEIGHT AND SUM
OFFA
WEIGHT AND SUM
DELAY
CASIN(12:0)
SUM CORRELATOR #1
CASOUT(8:0)
CASIN(12:0)
SUM
CASOUT(12:0)
DIN(3:0) DREF(3:0)
4 32-BIT CORRELATOR ************ SUM CORR SCORE
DOUT (3:0)
FIGURE 1. SINGLE CORRELATOR CONFIGURATION
OFFB
WEIGHT AND SUM
AUXOUT(8:0) CORRELATOR #2
FIGURE 2. DUAL CORRELATOR CONFIGURATION
7
HSP45256
The function performed by one correlation cell is: (Di,n XNOR Ri,n) AND Mi,n where: Di,n = Bit i of data register n Ri,n = Bit i of reference register n Mi,n = Bit i of mask register n The reference and mask bits are loaded sequentially, N bits at a time, where N depends on the current configuration (see Tables 2 and 9). New reference data is loaded on the rising edge of RLOAD and new mask data is loaded on the rising edge of CLOAD. The mask and reference bits are stored internally in Shift Registers, so that the mask and reference information that was loaded most recently will be used to process the newest data. When new information is loaded in, the previous contents of the mask and reference bits are shifted over by one sample, and the oldest information is lost. There are no registers in the multiplexer array (see Block Diagram), so the data on DOUT0-7 corresponds to the data in the last element of the correlation array. When monitoring DOUT0-7, AUXOUT0-8, and REFOUT0-7, only those bits listed in Table 9 are valid.
DREF RLOAD DCONT (MASK) CLOAD
>
R E G
A R E G B
DREFOUT
> >
R E G
DCONTOUT R E G
>
TXFR DATA CLK R E G
DATAOUT
>
COROUT
FIGURE 3. CORRELATION CELL BLOCK DIAGRAM
DCONT CLOAD
DATA CONTROL
DREF RLOAD A
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
DR8
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
TXFR B DR-1 DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7
DATA CLK
D-1
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 4. CORRELATION CELL TIMING DIAGRAM
8
HSP45256 Weight and Sum Logic
The Weight and Sum Logic provides the bit weighting and the final correlator score from the eight stages of the correlation array. For a 1 x 256 1-D configuration, the outputs of each of the stages are given a weight of 1 and then added together. In a 8 x 32 (8-bit data) configuration, the output of each stage will be shifted so that the output data represents an 8-bit word, with stage seven being the MSB. The 13-bit Offset Register is loaded from the control data bus. Its output is added to the correlation score obtained from the correlator array. This sum then goes to the programmable delay register data input. When the chip is configured as dual correlators, the user has the capability of loading two different offset values, one for each of the two correlators. The Programmable Delay Register sets the number of pipeline stages between the output of the weight and sum logic and the input of the Cascade Summer. This delay register is used to align the correlation scores of multiple correlators in HSP45256 cascaded configurations (see Applications Section). The number of delays is programmable from 1 to 16, allowing for up to 16 correlators to be cascaded. When the HSP45256 is configured as dual correlators, the delay must be set to 0000, which specifies a delay of 1.
Control Registers
The 3-bit address value, A0-2, is used to determine which internal register will be loaded with the data on DCONT0-7. The function is initiated when CLOAD is brought low, and the register is loaded on the rising edge of CLOAD. Table 1 indicates the function associated with each address. Tables 2 - 8 define the function of the bits in each of the control registers.
TABLE 1. ADDRESS MAPPING A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Mask Register Configuration Register Offset Register A-Most Significant Bits Offset Register A-Least Significant Bits Programmable Delay Register Offset Register B-Most Significant Bits Offset Register B-Least Significant Bits Reserved DESTINATION
Cascade Summer
The Cascade Summer is used for cascading several correlator chips together. The value present on this bus represents the correlation score from the previous HSP45256 that will be summed with the current score to provide the final correlation score. When several correlator chips are cascaded, the CASOUT0-12 of each correlator is connected to the CASIN0-12 of the next correlator in the chain. The CASIN0-12 of the first chip is tied low. The following function represents the correlation score present on CASOUT0-12 of each correlator: CASOUT(n) = (W7 x CO7)(n-Delay) + (W6 x CO6)(n-Delay) + (W5 x CO5)(n-Delay) + (W4 x CO4)(n-Delay) + (W3 x CO3)(n-Delay) + (W2 x CO2)(n-Delay) + (W1 x CO1)(n-Delay) + (W0 x CO0)(n-Delay) + Offset (n-Delay) + CASIN. where: CO0-CO7 are the correlation score outputs out of the correlation stages; W0-W7 is the weight given to each stage; n-Delay represents the delay on the weighted and summed correlation score through the Programmable Delay Register; Offset is the value programmed into the Offset register; CASIN is the cascade input.
9
HSP45256
TABLE 2. MASK REGISTER DESTINATION ADDRESS = 0 (000) BIT POSITIONS 7-0
FUNCTION Mask Register Bit Enable
DESCRIPTION MR(7:0): Mask Register. When mask register bit N = 1, the corresponding reference register bit is enabled. Mask register data is loaded from the DCONT(7:0) bus into a holding register on the rising edge of CLOAD and is written to the mask register on the rising edge of TXFR. TABLE 3. CONFIGURATION REGISTER DESTINATION ADDRESS = 1 (001)
BIT POSITION 7-6 5
FUNCTION Reserved TC Reserved; Program to zero.
DESCRIPTION
Configures correlator for twos complement input format, where the position of the MSB is depends on the current configuration. TC = 1 is twos complement; TC = 0 is offset binary. CONFIG4: The state of CONFIG4 configures the HSP45256 as either one or two correlators. When CONFIG4 = 0, the HSP45256 is configured as one correlator with the correlation score available on CASOUT0-12. When CONFIG4 = 1, the HSP45256 is configured as dual correlators with the first correlators score available on CASOUT0-8 and the second score available on AUXOUT0-8. When the chip is configured as dual correlators, the Programmable Delay must be set to 0000 for a delay of 1.
4
CONFIG(4)
3-2 1-0
CONFIG(3:2): CONFIG(1:0)
CONFIG(3:2): Control the number of data bits to be correlated. See Table 9. CONFIG(1:0): CONFIG1 and CONFIG0 represent the length of the correlation window as indicated in Table 9. TABLE 4. MS OFFSET REGISTER A DESTINATION ADDRESS = 2 (010)
BIT POSITION 7-5 4-0
FUNCTION Reserved Offset Register A MSB Reserved. Program to zero.
DESCRIPTION
OFFA(12:8): Most significant bits of Offset Register A. This is the register used in single correlator mode. TABLE 5. LS OFFSET REGISTER A DESTINATION ADDRESS = 3 (011)
BIT POSITION 7-0
FUNCTION Offset Register A LSB
DESCRIPTION OFFA(7:0): Least significant bits of Offset Register A. TABLE 6. PROGRAMMABLE DELAY REGISTER DESTINATION ADDRESS = 4 (100)
BIT POSITION 7-4 3-0
FUNCTION Reserved Programmable Delay Reserved. Program to zero.
DESCRIPTION
PDELAY(3:0): Controls amount of delay from the weight and sum logic to the cascade summer. The number of delays is 1-16, with PDELAY = 0000 corresponding to a delay of 1 and PDELAY = 1111 corresponding to a delay of 16.
10
HSP45256
TABLE 7. MS OFFSET REGISTER B DESTINATION ADDRESS = 5 (101) BIT POSITION 7-1 0
FUNCTION Reserved Offset Register B MSB Reserved. Program to zero.
DESCRIPTION
OFFB8: Most significant bit of Offset Register B. In dual correlator mode, this register is used for the correlator whose output appears on the AUXOUT pins. TABLE 8. LS OFFSET REGISTER B DESTINATION ADDRESS = 6 (110)
BIT POSITION 7-0
FUNCTION Offset Register B LSB
DESCRIPTION OFFB0-7: Least significant bits of Offset Register B.
11
TABLE 9. CONFIGURATION SETUP
CONFIGURATION NO. OF CORRELATORS 1 1 1 1 1 1 1 1 1 1 2 ACTIVE INPUTS DATA BITS 1 1 1 1 2 2 2 4 4 8 1 CORRELATOR A B A B A B A B A B A B ACTIVE OUTPUTS OUTPUT WEIGHTING
4 0 0 0
3 0 0 0 0 0 0 0 1 1 1 0
2 0 0 0 0 1 1 1 0 0 1 0
1 0 0 1 1 0 1 1 1 1 1 0
0 0 1 0 1 1 0 1 0 1 1 1
ROWS 1 2 4 8 1 2 4 1 2 1 1
LENGTH 256 128 64 32 128 64 32 64 32 32 128
DIN 7 7, 3 7, 5, 3, 1 7-0 7, 3 7, 5, 3, 1 7-0 7, 5, 3, 1 7-0 7-0 7 3 7, 5 3, 1 7-4 3-0 7, 5 3, 1 7-4 3-0 7-4 3-0
DREF 7 7, 3 7, 5, 3, 1 7-0 7 7, 5 7, 6, 5, 4 7 7, 6 7 7 3 7, 5 3, 1 7-4 3-0 7 3 7, 6 3, 2 7 3
DOUT 7 7, 3 7, 5, 3, 1 7-0 7, 3 7, 5, 3, 1 7-0 7, 5, 3, 1 7-0 7-0 7 3 7, 5 3, 1 7-4 3-0 7, 5 3, 1 7-4 3-0 7-4 3-0
AUXOUT 7 7, 3 7, 5, 3, 1 7-0 7, 3 7, 5, 3, 1 7-0 7, 5, 3, 1 7-0 7-0 8-0 8-0 8-0 8-0 8-0 8-0
CASOUT 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 -
CO7 1 1 1 1 2 2 2 8 8 128 1 1 1 2 2 8 -
CO6 1 1 1 1 2 2 2 8 8 8 1 1 1 2 2 2 -
CO5 1 1 1 1 2 2 2 2 2 32 1 1 1 1 1 4 -
CO4 1 1 1 1 2 2 2 2 2 4 1 1 1 1 1 1 -
CO3 1 1 1 1 1 1 1 4 4 64 1 1 1 2 2 8
CO2 1 1 1 1 1 1 1 4 4 2 1 1 1 2 2 2
CO1 1 1 1 1 1 1 1 1 1 16 1 1 1 1 1 4
CO0 1 1 1 1 1 1 1 1 1
12
0 0 0 0 0 0 0 1
HSP45256
1 1 1 1 1 1 1
1
0
0
1
0
2
1
2
64
1
0
0
1
1
2
1
4
32
1
0
1
1
0
2
2
1
64
1
0
1
1
1
2
2
2
32
1
1
0
1
1
2
4
1
32
HSP45256
During reference register loading, the 8-bits, DREF0-7 are used as reference data inputs. The falling edge of RLOAD initiates reference data loading; when RLOAD returns high, the data on DREF0-7 is latched into the selected correlation stages. The active bits on DREF0-7 are determined by the current configuration. The window configuration is determined by the state of control signals upon programming the Control Register. Table 9 represents the programming information required for each window configuration. In Table 9, note that the data listed for Output Weighting refers to the weights given to each of the Correlation Sum Outputs (CO0-7 in the Block Diagram). During initialization, the loading configuration for the reference data is set by the user. Table 9 shows the loading options. These load controls specify whether the reference data for a given stage comes from the shift register output of the previous stage or from an external data pin.
Applications
There are 10 single correlator configurations possible with the HSP45256. There are six dual correlator configurations possible with the HSP45256. Table 10 details the configuration (bits x rows x length) and the maximum correlation sums of all combinations.
TABLE 10. CORRELATION SCORE FORMULAS FOR SINGLE CORRELATOR CONFIGURATIONS CONFIGURATION BITS x ROWS x LENGTH 1 x 1 x 256 1 x 2 x 128 1 x 4 x 64 1 x 8 x 32 2 x 1 x 128 2 x 2 x 64 2 x 4 x 32 4 x 1 x 64 4 x 2 x 32 8 x 1 x 32 1 x 1 x 128 1 x 1 x 128 1 x 2 x 64 1 x 2 x 64 1 x 4 x 32 1 x 4 x 32 2 x 1 x 64 2 x 1 x 64 2 x 2 x 32 2 x 2 x 32 4 x 1 x 32 4 x 1 x 32 HIGHEST POSSIBLE TOTAL CORRELATION SCORE 256 256 256 256 384 384 384 960 960 8160 128 128 128 192 192 480
FIGURE NUMBER Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20
CORRELATION SCORE CS=CO7+CO6+CO5+CO4+CO3+CO2+CO1+CO0 CS=CO7+CO6+CO5+CO4+CO3+CO2+CO1+CO0 CS=CO7+CO6+CO5+CO4+CO3+CO2+CO1+CO0 CS=CO7+CO6+CO5+CO4+CO3+CO2+CO1+CO0 CS=2(CO7+CO6+CO5+CO4)+CO3+ CO2+CO1+CO0 CS=2(CO7+CO6+CO5+CO4)+CO3+CO2+CO1+CO0 CS=2(CO7+CO6+CO5+CO4)+CO3+CO2+CO1+CO0 CS=8(CO7+CO6)+4(CO5+CO4)+2(CO3+CO2)+CO1+CO0 CS=8(CO7+CO6)+4(CO5+CO4)+2(CO3+CO2)+CO1+CO0 CS=128C07+64CO6+32C05+16CO4+8CO3+4CO2+2CO1+CO0 CS=CO7+CO6+CO5+CO4CS=CO31CO2+CO1+CO0 CS=CO7+CO6+CO5+CO4CS=CO31CO2+CO1+CO0 CS=CO7+CO6+CO5+CORCS=CO31CO2+CO1+CO0 CS=2(CO7+CO6)+CO5+CO4CS=(CO3+CO2)+CO1+CO0 CS=2(CO7+CO6)+CO5+CO4CS=(CO3+CO2)+CO1+CO0 CS=8CO7+4CO6+2CO5+CO4CS= 8CO3+4CO2+2CO1+CO0
Single Correlator Configurations
1-Bit Data, Single Row, 256 Samples Configuration
A 1 x 256 (1-D configuration) correlation requires only 1 HSP45256. To initialize the correlator, all the reference bits, control bits, the delay value of the variable delay, and the window configuration must be specified. Table 11 details these settings for the 1-bit data, 256 Samples Configuration. Figure 5 illustrates the data flow through the correlator.
TABLE 11. REGISTER CONTENTS FOR 1 X 256 CORRELATOR WITH EQUAL WEIGHTING A0-2 001 DCONT0-7 00000000 NOTES 1 256-tap correlator: 1 x 256 window configuration, reference loaded from DREF7, eight stages weighted equally, DIN 7 and DOUT7 are the data input and output, respectively. Offset Register A = 0.
010 011 100 101 110
000000f00 00000000 00000000 00000000 00000000
Programmable Delay = 0. Offset Register B = 0 (Loading of this register optional in this mode).
13
HSP45256
The loading of the Reference and Mask Registers may be done simultaneously by setting A0-2 = 000, setting the DREF and DCONT inputs to their proper values and pulsing RLOAD and CLOAD low. In this configuration, DREF7 loads the reference data and DCONT7 loads the mask information; both sets of data are loaded serially. It will take 256 load pulses (RLOAD) to load the reference array, and 256 CLOAD pulses to load the mask array. Upon completion of the mask and register loading, TXFR is pulsed low, which transfers the reference and control data from the preload registers to the Reference and Mask Registers, updating the data that will be used in the correlation. Reference and mask data can be loaded more quickly by configuring the correlator as an 8 row by 32 sample array, loading the bits eight at a time, then changing the configuration back to 1 x 256 to perform the correlation.
REF <7> DATA <7> 7 6 5 4 3 2 1 0 REFOUT <7> DATAOUT <7>
1-Bit, Quad Row, 64 Sample Configuration
REF <7> DATA <7> 7 6 REF <5> DATA <5> 5 4 REF <3> DATA <3> 3 2 REF <1> DATA <1> 1 0 REFOUT <1> DATAOUT <1> REFOUT <3> DATAOUT <3> REFOUT <5> DATAOUT <5> REFOUT <7> DATAOUT <7>
CS = (CO7+CO6+CO5+CO4+CO3+CO2+CO1+CO0)
FIGURE 7. 1-BIT, 4 ROWS OF 64 TAPS
1-Bit, Octal Row, 32 Sample Configuration
REF <7> DATA <7> REF <6> DATA <6> REF <5> DATA <5> REF <4> DATA <4> REF <3> DATA <3> REF <2> DATA <2> REF <1> DATA <1> REF <0> DATA <0> 7 6 5 4 3 2 1 0 REFOUT <7> DATAOUT <7> REFOUT <6> DATAOUT <6> REFOUT <5> DATAOUT <5> REFOUT <4> DATAOUT <4> REFOUT <3> DATAOUT <3> REFOUT <2> DATAOUT <2> REFOUT <1> DATAOUT <1> REFOUT <0> DATAOUT <0>
CS = (CO7+CO6+CO5+CO4+CO3+CO2+CO1+CO0)
FIGURE 5. 1-BIT, 1 ROW OF 256 TAPS
CS = (CO7+CO6+CO5+CO4+CO3+CO2+CO1+CO0)
Other 1-Bit Configurations
1-Bit, Dual Row, 128 Sample Configuration
REF <7> DATA <7> 7 6 5 4 REF <3> DATA <3> 3 2 1 0 REFOUT <3> DATAOUT <3> REFOUT <7> DATAOUT <7>
FIGURE 8. 1-BIT, 8 ROWS OF 32 TAPS
2-Bit Configurations
2-Bit, Single Row, 128 Sample Configuration
REF <7> DATA <7> 7 6 5 4 DATA <3> 3 2 1 0 REFOUT <3> DATAOUT <3> REFOUT <7> DATAOUT <7>
CS = (CO7+CO6+CO5+CO4+CO3+CO2+CO1+CO0)
FIGURE 6. 1-BIT, 2 ROWS OF 128 TAPS
CS = 2(CO7+CO6+CO5+CO4)+(CO3+CO2+CO1+CO0)
FIGURE 9. 2 BITS, 1 ROW OF 128 TAPS
14
HSP45256
2-Bit Data, Dual Row, 64 Samples
REF <7> DATA <7> 7 6 REF <5> DATA <5> 5 4 DATA <3> 3 2 DATA <1> 1 0 REFOUT <1> DATAOUT <1> DATA <1> DATA <0> REFOUT <3> DATAOUT <3> DATA <3> DATA <2> REFOUT <5> DATAOUT <5> REFOUT <7> DATAOUT <7>
2-Bit, Quad Row, 32 Sample Configuration
REF <7> DATA <7> REF <6> DATA <6> REF <5> DATA <5> REF <4> DATA <4> 7 6 5 4 3 2 1 0 REFOUT <7> DATAOUT <7> REFOUT <6> DATAOUT <6> REFOUT <5> DATAOUT <5> REFOUT <4> DATAOUT <4> REFOUT <3> DATAOUT <3> REFOUT <2> DATAOUT <2> REFOUT <1> DATAOUT <1> REFOUT <0> DATAOUT <0>
CS = 2(CO7+CO6+CO5+CO4)+(CO3+CO2+CO1+CO0) CS = 2(CO7+CO6+CO5+CO4)+(CO3+CO2+CO1+CO0)
FIGURE 10. 2-BITS, 2 ROWS OF 64 TAPS
FIGURE 11. 2-BITS, 4 ROWS OF 32 TAPS
4-Bit Configurations
4-Bit, Single Row, 64 Sample Configuration
REF <7> DATA <7> 7 6 DATA <5> 5 4 DATA <3> 3 2 DATA <1> 1 0 REFOUT <1> DATAOUT <1> REFOUT <3> DATAOUT <3> REFOUT <5> DATAOUT <5> REFOUT <7> DATAOUT <7>
4-Bit Dual Row, 32 Sample Configurations
REF <7> DATA <7> REF <6> DATA <6> DATA <5> DATA <4> DATA <3> DATA <2> DATA <1> DATA <0> 7 6 5 4 3 2 1 0 REFOUT <7> DATAOUT <7> REFOUT <6> DATAOUT <6> REFOUT <5> DATAOUT <5> REFOUT <4> DATAOUT <4> REFOUT <3> DATAOUT <3> REFOUT <2> DATAOUT <2> REFOUT <1> DATAOUT <1> REFOUT <0> DATAOUT <0>
CS = 8(CO7+CO6)+4(CO5+CO4)+2(CO3+CO2)+(CO1+CO0)
CS = 8(CO7+CO6)+4(CO5+CO4)+2(CO3+CO2)+(CO1+CO0)
FIGURE 12. 4-BITS, 1 ROW OF 64 TAPS
FIGURE 13. 4 BITS, 2 ROWS OF 32 TAPS
15
HSP45256 8-Bit Configurations
8-Bit Data, Single Row, 32 Sample Configurations
An 8 x 32 correlation also requires only 1 HSP45256. To initialize the correlator, all the reference bits, control bits, the value of the programmable delay, and the window configuration must be specified. Table 12 details these settings. Again, the loading of the reference and mask registers can be done simultaneously. Due to the programming initialization, DREF0-7 are used to load the reference data 8bits at a time. It will take 32 load pulses each of RLOAD and CLOAD to load both arrays. Upon completion of the mask and register loading, TXFR is pulsed low, which transfers the reference and control data from the preload registers to the registers that store the active data. This configuration performs correlation of an 8-bit number with a 1-bit reference. Each byte out of the correlation array gives an 8-bit level of confidence that the data corresponds to the reference. The correlation score is the sum of these confidence levels.
REF <7> DATA <7> DATA <6> DATA <5> DATA <4> DATA <3> DATA <2> DATA <1> DATA <0> 7 6 5 4 3 2 1 0
TABLE 12. REGISTER LOADING FOR 8 X 32 CORRELATOR WITH BINARY WEIGHTING A0-2 001 DCONT0-7 00001111 NOTES 1 256-tap correlator; 8 x 32 window configuration, 8-bit data stream; reference register is loaded from DREF7 for all stages. Correlator score = (128 x CO7) + (64 x CO3) + (32 x CO5) + (16 x CO1) + (8 x CO6) + (4 x CO4) + (2 x CO2) + CO0. Offset Register A = 0000000010000.
010 011 100 101 110
00000000 00010000 00000000 00000000 00000000
Programmable Delay = 0. Offset Register B = 0 (Loading optional in this mode).
REFOUT <7> DATAOUT <7> REFOUT <6> DATAOUT <6> REFOUT <5> DATAOUT <5> REFOUT <4> DATAOUT <4> REFOUT <3> DATAOUT <3> REFOUT <2> DATAOUT <2> REFOUT <1> DATAOUT <1> REFOUT <0> DATAOUT <0>
CS = 128CO7+64CO6+32CO5+16CO4+8CO3+4CO2+2CO1+CO0
FIGURE 14. 8 BITS, 1 ROW OF 32 TAPS
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HSP45256 Dual Correlator Configurations
1-Bit, Single Row, 128 Sample Configuration
REF <7> DATA <7>
7 6 5 4 DATAOUT <7>
REF <3> DATA <3>
3 2 1 0 DATAOUT <3>
CSA = (CO7+CO6+CO5+CO4); (CASOUT)
CSB = (CO3+CO2+CO1+CO0); (AUXOUT)
FIGURE 15. DUAL 1-BIT, 1 ROW OF 128 TAPS
1-Bit, Dual Row, 64 Sample Configuration
REF <7> DATA <7> REF <3> DATA <3> DATAOUT <7> REF <1> DATA <1> DATAOUT <5>
7 6
3 2 1 0 DATAOUT <1> DATAOUT <3>
REF <5> DATA <5>
5 4
CSA = (CO7+CO6+CO5+CO4); (CASOUT)
CSB = (CO3+CO2+CO1+CO0); (AUXOUT)
FIGURE 16. 1-BIT, 2 ROWS OF 64 TAPS
1-Bit, Quad Row, 32 Sample Configuration
REF <7> DATA <7> REF <6> DATA <6> REF <5> DATA <5> REF <4> DATA <4> REF <3> DATA <3> REF <2> DATA <2> REF <1> DATA <1> REF <0> DATA <0>
7 6 5 4
DATAOUT <7> DATAOUT <6> DATAOUT <5> DATAOUT <4>
3 2 1 0
DATAOUT <3> DATAOUT <2> DATAOUT <1> DATAOUT <0>
CSA = (CO7+CO6+CO5+CO4); (CASOUT)
CSB = (CO3+CO2+CO1+CO0); (AUXOUT)
FIGURE 17. 1-BIT, 4 ROWS OF 32 TAPS
17
HSP45256
2-Bit, Dual Row, 64 Sample Configuration
Dual 2 x 64 correlators require only one HSP45256. To initialize the correlator, all the reference bits, control bits, the delay value of the variable delay, and the window configuration must be specified. Table 13 details the settings for the 2-bit Dual Row, 64 Sample Configuration.
REF <7> DATA <7>
In this example, each of the dual correlators compares 2-bit data to a 1-bit reference. It will take 64 load pulses (RLOAD/CLOAD) to completely load the reference and mask registers in the array. The programmable delay must be set to 0 for the output of the two correlators to be aligned.
7 6 DATAOUT <7>
REF <3> DATA <3>
3 2 DATAOUT <3>
DATA <5>
5 4 DATAOUT <5>
DATA <1>
1 0 DATAOUT <1>
CSA = 2(CO7+CO6)+CO5+CO4); (CASOUT)
CSB = 2(CO3+CO2)+CO1+CO0); (AUXOUT)
FIGURE 18. 2-BITS, 1 ROW OF 64 TAPS TABLE 13. REGISTER LOADING FOR DUAL 2 X 64 CORRELATORS WITH EQUAL WEIGHTING AO-2 001 DCONT0-7 00010110 NOTES Dual correlators: Each 2 bit data, 64 taps; reference register for correlation A is loaded from DREF7 and DREF5, the reference register for correlator B is loaded from DREF3 and DREF1. Correlator #1 = 2x C07 + 2 x CO6 + CO5 + CO4, correlator #2 = 2 x CO3 + 2x CO2 + CO1 + CO0. Offset Register A = 0000000010000.
010 011 100 101 110
00000000 00010000 00000000 00000000 00000000
Programmable Delay = 0. Offset Register B = 0.
2-Bit, Dual Row, 32 Sample Configuration
REF <7> DATA <7> REF <6> DATA <6> DATA <5> DATA <4> 7 6 5 4 DATAOUT <7> DATAOUT <6> DATAOUT <5> DATAOUT <4> REF <3> DATA <3> REF <2> DATA <2> DATA <1> DATA <0> 3 2 1 0 DATAOUT <3> DATAOUT <2> DATAOUT <1> DATAOUT <0>
CSA = 2(CO7+CO6)+CO5+CO4); (CASOUT)
CSB = 2(CO3+CO2)+CO1+CO0); (AUXOUT)
FIGURE 19. 2-BITS, 2 ROWS OF 32 TAPS
4-Bit, Single Row, 32 Sample Configuration
REF <7> DATA <7> DATA <6> DATA <5> DATA <4> 7 6 5 4 DATAOUT <7> DATAOUT <5> DATAOUT <5> DATAOUT <4> REF <3> DATA <3> DATA <2> DATA <1> DATA <0> 3 2 1 0 DATAOUT <3> DATAOUT <2> DATAOUT <1> DATAOUT <0>
CSA = 8(CO7)+4(CO6)+2(CO5)+(CO4); (CASOUT)
CSB = 8(CO3)+4(CO2)+2(CO1)+(CO0); (AUXOUT)
FIGURE 20. 4-BITS, 1 ROW OF 32 TAPS
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HSP45256
Cascading Multiple Correlator Devices
Correlators can be cascaded in either a serial or parallel fashion. Longer correlations can be achieved by connecting several correlators together as shown in Figures 21- 23. In Figure 21, each correlator is in a one data bit, one row, 256 tap configuration. The number of bits of significance at the CASOUT output of each correlator builds up from one correlation to the next, that is, the maximum score out of the first correlator is 256, the maximum output of the second correlator is 512, etc. In this configuration, the maximum length of the correlation is 4096. This would be implemented with 16 HSP45256's. The Programmable Delay Register in the first correlator would be set for one delay, the second would be set for two, and so on, with the final HSP45256 being set for a delay of 16. Correlations of more bits can be calculated by connecting CASOUT of each chip to the CASIN of the following chip (Figure 21). The data on the CASOUT lines accumulates in a similar manner as in the 1 x 256 mode, except that the maximum output of the first correlator is decimal 960, (hexadecimal 3C0); in the general case, the maximum number of correlators that can be cascaded in this manner is eight, since the maximum output of the last one would be 1E00, which nearly uses up the 13-bit range of the cascade summer. More parts could be cascaded together if some bits are to be masked out or if the user has a prior knowledge of the maximum value of the correlation score. As before, the delay in the first correlator would be set to one, the second correlator would be set for a delay of two, and so on. Multiple HSP45256's can be cascaded for two dimensional one bit data (Figure 22). The maximum output for each chip is the same as in the 1 x 256 case; the only difference is in the manner in which the correlators are connected. The programmable delay registers would be set as before.
DATA INPUT DIN7 CASIN0-12 DOUT7 CASOUT0-12 DIN7 CASIN0-12 DOUT7 CASOUT0-12 DIN7 CASIN0-12 DOUT7 CASOUT0-12 DIN7 CASIN0-12 DOUT7 CASOUT0-12 CORRELATOR SCORE OUTPUT
FIGURE 21. 1-BIT, 1024 SAMPLE CONFIGURATION
DATA INPUT DIN7, 5, 3, 1 DOUT7, 5, 3, 1 CASIN0-12 CASOUT0-12 DIN7, 5, 3, 1 DOUT7, 5, 3, 1 CASIN0-12 CASOUT0-12 DIN7, 5, 3, 1 DOUT7, 5, 3, 1 CASIN0-12 CASOUT0-12 DIN7, 5, 3, 1 DOUT7, 5, 3, 1 CASIN0-12 CASOUT0-12 CORRELATOR SCORE OUTPUT
FIGURE 22. 4-BIT, 256 SAMPLE CONFIGURATION
DATA INPUT ROWS 0 - 7 DIN0-7 CASIN0-12 CASOUT0-12
DATA INPUT ROWS 8 - 15 DIN0-7 CASIN0-12 CASOUT0-12
DATA INPUT ROWS 16 - 23 DIN0-7 CASIN0-12 CASOUT0-12
DATA INPUT ROWS 24 - 31 DIN0-7 CASIN0-12 CASOUT0-12 CORRELATOR SCORE OUTPUT
FIGURE 23. 1-BIT, 32 x 32 WINDOW CONFIGURATION
19
HSP45256 Reloading Data During Operation
RLOAD and CLOAD are asynchronous signals that are designed to be driven by the memory interface signals of a microprocessor. TXFR is synchronized to CLK so that the mask or reference data is updated on a specific clock cycle. In the normal mode of operation, the user loads the reference and mask memories, then pulses TXFR to use that data. The correlator uses the new mask or reference information immediately. Loading of the reference and mask data remains asynchronous as long as there is at least one cycle of CLK between the rising edge of RLOAD or CLOAD and the TXFR pulse. If the system timing makes it necessary for TXFR and RLOAD and/or CLOAD to be active during the same clock cycle, then they must be treated as synchronous signals; the timing for this case is shown in Figure 24 and given in the AC Timing Specifications (tTHCL and tCLLH). In this example, data is loaded during clock cycle 1 and transferred on the rising edge of CLK that occurs in clock cycle two. Another set of data is loaded during clock cycle 2, which will be transferred by a later TXFR pulse. The sequence of events is as follows: 1. In clock cycle 1, TXFR becomes active at least tTH nanoseconds after the rising edge of CLK. 2. RLOAD and/or CLOAD pulses low; the timing is not critical as long as its rising edge occurs before the end of clock cycle 1. If this condition is not met, it is undetermined whether the data loaded by this pulse will be transferred by the current TXFR pulse. 3. The rising edge of TXFR occurs while CLK is high during clock cycle 2. The margin between the rising edge of TXFR and the falling edge of CLK is defined by tTHCL. 4. RLOAD and/or CLOAD pulses low. The rising edge of RLOAD and CLOAD must occur after the falling edge of CLK. The margin between the two is defined by tCLLH. The time from the rising edge of TXFR to the falling edge of CLK must be greater than tTHCL, and the time from the falling edge of CLK to the rising edge of RLOAD or CLOAD must be greater than ts. If this timing is violated, the data being transferred by the TXFR pulse shown may or may not include the data loaded in clock cycle 2.
CLOCK CYCLE 1
CLOCK CYCLE 2
CLK tTH 1.
TXFR tTHCL 3. RLOAD, CLOAD 2. tCLLH 4.
FIGURE 24. LOADING AND TRANSFERRING DATA DURING THE SAME CLOCK CYCLE
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HSP45256
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PLCC Package. . . . . . . . . . . . . . . . . . . 34 PGA Package. . . . . . . . . . . . . . . . . . . . 36 10 Maximum Package Power Dissipation Commercial PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.9W Commercial PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.3W Industrial PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.9W Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13,000 Gates
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Temperature Range Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER Logical One Input Voltage Logical Zero Input Voltage High Level Clock Input Low Level Clock Input Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Standby Power Supply Current Operating Power Supply Current SYMBOL VIH VIL VIHC VILC VOH VOL II IO ICCSB ICCOP VCC = 5.25V VCC = 4.75V VCC = 5.25V VCC = 4.75V IOH = 400A, VCC = 4.75V IOL = +2.0mA, VCC = 4.75V VIN = VCC or GND, VCC = 5.25V VOUT = VCC or GND, VCC = 5.25V VIN = VCC or GND, VCC = 5.25V f = 25.6MHz, VIN = VCC or GND, VCC = 5.25V, Note 2, 4 TEST CONDITIONS MIN 2.0 3.0 2.6 -10 -10 MAX 0.8 0.8 0.4 10 10 500 179 UNITS V V V V V V A A A mA
Capacitance
TA = 25oC, Note 3 SYMBOL CIN CO MIN MAX 10 10 UNITS pF pF TEST CONDITIONS Frequency = 1MHz, VCC = Open All measurements are referenced to device ground.
PARAMETER Input Capacitance Output Capacitance NOTES:
2. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 7mA/MHz. 3. Not tested, but characterized at initial design and at major process/design changes. 4. Output load per test load circuit and CL = 40pF.
AC Electrical Specifications
PARAMETER CLK Period CLK High CLK Low
VCC = 5.0V
5%, TA = 0oC to 70oC, TA = -40oC to 85oC, Note 5
33MHz 25.6MHz MIN 39 15 15 MAX UNITS ns ns ns NOTES MIN 30 12 12 MAX -
SYMBOL t CP t CH t CL
21
HSP45256
AC Electrical Specifications
PARAMETER Set-Up Time DIN to CLK High Hold Time CLK High to DIN TXFR Set-Up Time TXFR Hold Time Output Delay DOUT, AUXOUT, CASOUT CLOAD Cycle Time CLOAD High CLOAD Low Set-Up Time, A to RLOAD, CLOAD Hold Time, RLOAD, CLOAD to A RLOAD Cycle Time RLOAD High RLOAD Low Set-Up Time, DCONT to CLOAD Hold Time, CLOAD to DCONT Set-Up Time, DREF to RLOAD Hold Time, RLOAD to DREF Output Enable Time Output Disable Time Output Rise, Fall Time TXFR High to CLK Low CLK Low to RLOAD, CLOAD High NOTES: 5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; Input levels (all other inputs) 0V and 3.0V; Timing reference levels (CLK) 2.0V; All others 1.5V. Output load per test load circuit with CL = 40pF. Output transition is measured at VOH > 1.5V and VOL < 1.5V. 6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. VCC = 5.0V
5%, TA = 0oC to 70oC, TA = -40oC to 85oC, Note 5 (Continued)
33MHz 25.6MHz MIN 13 0 13 0 39 15 15 13 0 39 15 15 13 0 13 0 MAX 20 15 15 6 3 1 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES MIN 12 0 12 0 30 12 12 12 0 30 12 12 12 0 12 0 Note 6 Note 6 Note 6 Note 6 3 1 MAX 15 15 15 6 -
SYMBOL t DS t DH t TS t TH t DO t CLC t CLH t CLL t AS t AH t RLC t RLH t RLL t DCS t DCH t RS t RH t OE t OD t RF t THCL t CLLH
Test Load Circuit
S1 DUT
CL
IOH
INCLUDES STRAY
AND JIG CAPACITANCE
1.5V
IOL
EQUIVALENT CIRCUIT SWITCH S1 OPEN FOR ICCSB AND ICCOP TEST
22
HSP45256 Timing Waveforms
t CP t CH CLK t DS t DH t CLH DIN0-7 CLOAD t TS t TH t TS t AS t AH A0-2 t DO DOUT0-7 CASOUT0-12, AUXOUT0-8 DCONT0-7 t CS t CH t CLC t CLL t CL
TXFR
FIGURE 25. INPUT, OUTPUT TIMING
FIGURE 26. CONTROL INPUT TIMING
t RLC t RLL DLOAD t AS t AH A0-2 t RS t RH DREF0-7 DOUT0-7, CASOUT0-12, AUXOUT0-8 t r, t f 0.8V 2.0V AUXOUT0-8 CASOUT0-12 t RLH OEA, OEC t OD t OE 1.7V 1.3V
FIGURE 27. REFERENCE INPUT TIMING
FIGURE 28. OUTPUT TIMING
t THCL t CLLH
CLK
TXFR
RLOAD, CLOAD
FIGURE 29. TRANSFER, LOAD TIMING WHEN BOTH OCCUR ON A SINGLE CYCLE
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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